1. Field of the Invention
The present invention relates to a semiconductor device containing a voltage-drive type insulating gate bipolar transistor (hereinafter referred to as an IGBT) for use in a power converter such as an inverter.
2. Prior Art
A diode, which is connected in opposite to a directional semiconductor element in such a manner that the main current flowing through the directional semiconductor element flows in a reverse direction through the diode, has been known as a freewheeling diode (hereinafter referred to as an FWD).
FIG. 1 shows such an FWD and an IGBT. In an IGBT chip 10, a p well 2 is formed on one surface of an n layer 1, and n emitter layers 3 are also formed in the surface of the p well 2. A gate oxide film 5 is formed on a channel portion 4 which is in the surface of the p well 2 and intervenes between the exposure portion of the n layer 1 and the n emitter layer 3, and a gate terminal G is connected to a gate electrode 6 on the gate oxide film 5. An emitter electrode 7 is formed by an A1 vacuum evaporation so as to be commonly brought in contact with the surfaces of the p well 2 and the n emitter layers 3. A collector electrode 9 is formed so as to be brought into contact with a p emitter layer 8 which is formed on the opposite surface of the n layer 1 from the emitter electrode. A p well 11 in which the n emitter layer 3 is not contained is also formed on the n layer 1, and a pad portion 12 is formed on the p well 11. Further, p-type guard rings 13 are formed on the edge portion of the IGBT chip 10, at two stages in this case, to improve a voltage blocking capability.
On the other hand, in an FWD chip 20, a p+ anode region 22 is formed on one surface of an n layer 21, and an anode electrode 23 is formed by an A1 vacuum evaporation so as to be brought into contact with the surface of the p+ anode region 22. A cathode electrode 25 is formed so as to be brought into contact with an n+ region 24 which is formed on the other surface of the n layer 21. Similarly to the case of the IGBT chip 10, p-type guard rings 26 are provided on the edge portion of the n layer 21. The cathode electrode 25 of the FWD chip 20 as well as the collector electrode 9 of the IGBT chip 10 are soldered with a metal plate in a package of the chips, and connected to a common collector terminal C. On the other hand, the pad portion 12 of the IGBT chip 10 and the anode electrode 23 of the FWD chip 20 are connected to an emitter terminal E through respective A1 wires 27.
In the case where both the IGBT chip 10 and the FWD chip 20 shown in FIG. 1 are deposited in one package, a gap must be provided between these two chips for providing not only an insulation distance necessary for a voltage blocking capalitity, but also a room for allowing displacement of chips at soldering and for fitting solder fillets along chip sides. Moreover, some space is required for accommodating the A1 wires 27 which connect the pad portion 12 and the anode electrode 23 to the emitter terminal E. Therefore, it is difficult to arrange the IGBT chips 10 and the FWD chips 20 in a package with high packing density for obtaining a high power density. In addition, because a wiring is performed by bonding the aluminum conductor 27, an inductance in the package is increased and deviation of the inductance between the chips becomes large. Hence, it is difficult to realize high speed operation and a large turn-off current capability of the semiconductor device.